The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. High packing density, low heat generation, low power consumption, and good reliability must be maintained without any functional device degradation.
Commonly, device manufacturers specify or define a number of boundary operational parameters (e.g., max/min voltage, max/min current, max/min temperature) within which a desired device reliability level may be achieved, or even guaranteed. For example, a semiconductor device may be guaranteed an operational life of 10 years if its supply voltage is maintained at or below 5 Volts over that life. Frequently, however, end equipment applications may, intentionally or not, require a semiconductor device to operate at some value outside the specified boundary parameters for a period (or periods) of time. This operational overstress may degrade the performance or lifetime of the device, or may cause complete device failure. In either case, system reliability is impacted significantly.
One such overstress problem, frequently encountered, involves over-voltage effects on semiconductor dielectrics—particularly oxides. Depending upon the structures and processes with which a device is formed, certain dielectric structures and substructures can be especially susceptible to over-voltage damage. Consider, for example, a gate oxide implemented in a MOSFET structure. Over-voltage operation can cause anomalies in a gate oxide (e.g., cracks, breaks)—anomalies that can alter or ruin the functionality of the FET.
As a result, devices utilized in such applications are often tested, either during production or immediately thereafter, to screen out devices that are likely to break down under certain over-voltage conditions. One such integrity screening involves measurement of leakage current through an oxide structure undergoing over-voltage stress. For example, a gate oxide structure may be stressed to some multiple (e.g., 125%, 150%, 200%) of the specified maximum voltage for that structure. Leakage currents through the gate structure are measured at various points throughout the stress test, and compared. If leakage current variations exceed some predetermined threshold, then the device is rejected.
Unfortunately, depending upon the specific circuitry implemented in the semiconductor device, there are often a number of device structures and substructures that interfere with or prevent the screening tests referenced above. Circuitry coupled to the gate of a FET (e.g., power-off discharge circuitry) can create alternative leakage paths that skew the outcome of an over-voltage stress test. Some devices may incorporate circuitry (e.g., Zener diode) that couples the gate and the source of a FET together—limiting the extent to which the gate oxide may be stressed. Certain devices lack blocking circuitry between the so gate and an operational supply that drives the gate during normal operation. Thus, during gate oxide testing, a current path exists that may charge the supply—again limiting the extent to which the gate oxide may be stressed.
As a result, there is a need for an oxide stress testing system that effectively and accurately assesses overstress integrity of oxide structures—providing reliable device characterization in an easy, efficient and cost-effective manner.